1. Technical Field
The present disclosure relates to a clock divider and, more particularly to a clock divider capable of producing different output signals based on various division ratios.
2. Discussion of Related Art
Generally, a clock divider is used in a phase locked loop (PLL) circuit or a clock generating circuit. A clock generating circuit may be formed as a separate integrated circuit (chip) or formed as part of a larger chip to provide clock signals internally or externally. A clock divider used in a PLL may generate different clock signals of various division ratios. Conventional clock dividers include a plurality of clock dividers having predetermined division ratios and a multiplexer for selecting and outputting a divided clock signal generated by one of the clock dividers.
In the conventional clock dividers that include a plurality of clock dividers having various division ratios, the chip size is increased in proportion to the number of clock division ratios and the power consumption is increased. In addition, a glitch may occur when a division ratio of an output signal is changed in the conventional clock divider. An additional circuit such as a glitch filter may be necessary for preventing the glitch, which further increases the chip size and power consumption.